Senior ASIC Ethernet Design Engineer - Cornelis Networks (Remote)

**Overview**

Cornelis Networks is seeking a Senior ASIC Ethernet Design Engineer to join our innovative team building world-class networking solutions for AI and HPC datacenters. As a leader in high-performance scale-out networking, we deliver differentiated architecture that seamlessly integrates hardware, software, and system technologies to maximize efficiency in GPU, CPU, and accelerator-based compute clusters. Join our fast-growing, global team spanning multiple countries as we solve the world's most demanding computational challenges.

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Responsibilities **

• Lead complete SoC/ASIC development lifecycle from concept to deployment • Execute front-end standard cell ASIC development including RTL creation, design verification, synthesis, and post-silicon validation • Collaborate with diverse internal and external teams across all organizational levels • Design, implement, troubleshoot, and deliver comprehensive system solutions utilizing purpose-built ASICs • Drive innovation in high-performance computing, data analytics, and AI interconnect solutions

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Requirements **

• Bachelor's degree in Computer Engineering, Computer Science, or Electrical Engineering (Master's preferred) • 15+ years post-graduation experience in silicon development and digital design using HDL languages (System Verilog, Verilog, VHDL) • 10+ years networking hardware design experience with proven expertise in 50G, 100G, 400G Ethernet MAC/PCS protocols, TCP/IP, RDMA/RoCE, IPSec • 5+ years experience with scripting languages (TCL, Python, Perl) • Deep understanding of Standard Cell ASIC development flow including digital design, IP integration, simulation, and synthesis • Track record of first-pass ASIC success and experience with multiple clock designs and asynchronous interfaces preferred

This fully remote position supports US-based candidates with occasional travel opportunities.

Monday to Friday, 9 AM – 5 PM (full-time)