Staff Digital Design Engineer - CPU Architecture & RISC-V at Innatera

**Overview**

Innatera is seeking an experienced Staff Digital Design Engineer to spearhead technical leadership in RISC-V CPU architecture and subsystem integration for cutting-edge neuromorphic SoCs. This remote position offers the opportunity to drive architectural innovation from concept through final implementation, working with advanced CPU cores and digital IP development.

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Responsibilities **

• Architect and develop sophisticated CPU cores and micro-architectures, specializing in RISC-V instruction sets and custom extensions • Convert high-level architectural vision into comprehensive micro-architectural specifications for CPU implementations • Partner with verification teams to establish thorough testing protocols and validate CPU IP performance and instruction set compliance • Establish SoC-level architectural frameworks, emphasizing seamless CPU core integration with complementary IP blocks and subsystems • Support SoC functionality validation through comprehensive top-level testing to guarantee optimal system performance • Execute RTL development and troubleshooting for CPU cores using Verilog or System Verilog • Perform detailed RTL and gate-level simulations to verify design precision and performance metrics • Complete front-end design workflows including synthesis, static timing analysis, and formal equivalence verification • Champion software-hardware co-design initiatives with deep system-level understanding • Pioneer innovative CPU IP development based on product requirements and emerging architectural concepts • Assess and integrate third-party CPU components to optimize overall system capabilities

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Requirements **

• 7+ years in digital design with specialized focus on CPU architecture and micro-architecture development • Proven track record designing and implementing RISC-V CPU cores • Comprehensive knowledge of CPU pipeline architectures, memory systems, interrupt mechanisms, and bus interfaces • Advanced RTL coding proficiency in Verilog/System Verilog for complex digital systems • Strong SoC architecture expertise with emphasis on CPU integration •

Experience with front-end design processes including synthesis and timing analysis • Solid background in digital verification methodologies and cross-team collaboration

Monday to Friday, 9 AM – 5 PM (full-time)