In the role of Senior Principal ASIC Design Engineer at Astera Labs, you will be primarily responsible for guiding the ASIC design process for advanced Ethernet and Scale-Up connectivity products. Your key responsibilities will include defining and driving ASIC architecture, leading RTL design, and executing from architecture through to post-silicon validation. A minimum of 12 years’ experience in ASIC/SoC design, particularly in high-speed networking, is required.