Senior PCIe ASIC Design Engineer - Cornelis Networks (Remote)

**Overview**

Cornelis Networks is seeking a Senior ASIC Design Engineer to spearhead PCIe controller design and integration for cutting-edge SoCs. Join our global team delivering world-class scale-out networking solutions for AI and HPC datacenters. We're a fast-growing company backed by top-tier investors, combining hardware, software, and system technologies to maximize compute cluster efficiency at any scale.

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Responsibilities **

• Lead complete PCIe IP integration lifecycle within complex ASIC architectures • Partner with IP vendors, architecture, verification, physical design, and software teams to deliver robust PCIe subsystems • Spearhead performance optimization initiatives across the PCIe stack, from PHY tuning to DMA/transaction layer efficiency • Contribute strategic insights to system architecture and microarchitecture planning, emphasizing IO and interconnect scalability • Direct silicon bring-up and PCIe link validation in laboratory environments, coordinating with board and firmware specialists • Troubleshoot functional and performance challenges at RTL, gate-level, and silicon stages • Maintain PCIe specification compliance and support interoperability testing initiatives • Mentor junior engineering talent and establish PCIe subsystem development standards • Apply expertise in high-bandwidth, low-latency connectivity for high-performance compute platforms

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Requirements **

• BS/MS in Electrical Engineering, Computer Engineering, or related discipline • 10+ years of ASIC/SoC design experience specializing in PCIe controller integration • Demonstrated silicon bring-up and high-speed interface debugging expertise • Comprehensive knowledge of PCIe protocol stack (PHY, MAC, TLP, DLL), configuration space, and link training • Practical experience with PCIe verification environments, performance optimization, and power-conscious design • Proficiency with PCIe compliance testing, simulation tools (VCS, Questa), and lab equipment (protocol analyzers, oscilloscopes) • Advanced scripting capabilities (Python, Perl, TCL) and debugging proficiency • Exceptional verbal and written communication abilities

Monday to Friday, 9 AM – 5 PM (full-time)